Methods and Architectures for Realizing Fast Phylogenetic Computation Engines Using VLSI Array Based Logic

Evaluating phylogenetics trees is an endeavor fundamental to comparative genomics and a core discipline of Bioinformatics. However, with single trees taking up to a week on the fastest processor under general models of evolution and the number of trees growing exponentially with the number of sequences analyzed, this is an exceptionally computationally intensive endeavor. There has been much work recently to develop more efficient algorithms, as well as to parallelize algorithms for execution on fast and/or distributed computing platforms. However, it is apparent that these approaches can only lessen the problem, as computational run-times remain on the order of weeks for likelihood-type approaches in particular, which are a favorite because of their biological and statistical appeal. At present, phylogenetics algorithms are still executing code running on many layers of other software, before actually executing on the underlying computational hardware. We propose a design method plus a set of architecture patterns for implementing phylogenetics algorithms directly into hardware, thus eliminating much overhead and allowing for on-chip parallelization. The solution formulations use a direct mapping to applicationspecific, VLSI array-based custom computing machines design specifically for phylogenetics data processing tasks. Such VLSI computing “engines” are realized as specialized computer chips that can either be integrated with standard computing platforms (e.g., with PCs as add-on cards) or used to construct specialized computing environments for bioinformatics and genomics data processing.